1. Field of the Invention
The present invention relates to a voltage generating circuit for generating a voltage higher than an operating voltage, and more particularly, to a charge pump circuit applied appropriately to a semiconductor memory device.
2. Description of the Related Art
Semiconductor memory devices in recent times tend to have an operating voltage that is lowered to reduce power consumption. But some circuit portions of semiconductor memory, e.g., word line drivers or output drivers, require a high voltage higher than the operating voltage. Thus, charge pump circuits are equipped with most semiconductor memory chips.
Examples of various charge pump circuits are disclosed in U.S. Patent Application Publication No. US2004/0027102 (Kyu-Hong Kim). In this patent application, a charge pump circuit disclosed as the conventional technique is constructed of the plurality of inverters I1, I2, I3, and I4, capacitors C1, C2, and C3, and NMOS transistors N1-N6, as shown in FIG. 1. When signals CON1 and CON2, shown in FIG. 2, are respectively applied to the inverters I1 and I2, and when the voltage at node A is larger than VCC+Vth, the voltage at node B increases to VCC and is then boosted to 2VCC, as in waveform B shown in FIG. 2, by operation of the capacitor C2. Meanwhile, node C has a voltage of VCC when the output voltage of the inverter 13 becomes greater than VCC+Vth, and is then boosted to VCC+VPP, as in waveform C, shown in FIG. 2, by operation of the capacitor C3. NMOS transistor N6 performs the charge sharing operation between node B and a high voltage generation terminal VPP in response to the voltage at node C. In NMOS transistor N6, the bulk (i.e., the substrate) is at a ground voltage and the source is at the high voltage VPP or voltage 2VCC, and the voltage difference between the source and the bulk becomes VPP or 2VCC. Thus the threshold voltage Vth of the NMOS transistor N6 can increase hundreds of times more than when the voltage difference between the source and the substrate is zero.
Meanwhile, the voltage applied to the gate of the NMOS transistor N6 maintains the voltage VPP+VCC, so the charge transmission efficiency between node B and the high voltage generation terminal VPP is lowered. That is, the charge transmission transistor N6 constructed of an NMOS transistor transfers the charge of node B to the high voltage generation terminal VPP in response to the voltage of control node C in the charge pumping operation. Meanwhile, in the charge pump circuit of FIG. 1, the bulk voltage of the charge transmission transistor N6 is fixed to the ground voltage, and in this state the source voltage increases during the boosting operation. Hence, the threshold voltage of the charge transmission transistor N6 increases by the body effect. The charge of boosting node B is difficult to sufficiently transfer to the high voltage generation terminal VPP since the gate voltage of the charge transmission transistor N6 is still fixed even though the threshold voltage becomes large.
The patent application described above discloses an improved charge pump circuit, shown in FIG. 3, to solve the problem of the charge pump circuit of FIG. 1. That is, the circuit of FIG. 3 uniformly maintains the voltage difference between the source and the bulk or substrate of the NMOS transistor N6 shown in FIG. 1 so as not to increase the threshold voltage. FIG. 3 depicts a configuration that includes NMOS transistors N7 and N8, which are added to the configuration of the circuit shown in FIG. 1.
In FIG. 3, the drain of the NMOS transistor N7 is connected to the drain of NMOS transistor N6, the gate of the NMOS transistor N7 is connected to the high voltage generation terminal VPP, and the source of the NMOS transistor N7 is connected to node D. The source of the NMOS transistor N8 is connected to node D, the gate of the NMOS transistor N8 is connected to node B, and the drain of the NMOS transistor N8 is connected to the high voltage generation terminal VPP. Node D is connected to the bulk or substrate of the NMOS transistor N6.
Operation of the charge pump circuit shown in FIG. 3 will now be described, based on the functions of newly added NMOS transistors N7 and N8.
When signals CON1 and CON2 having the ground voltage are applied, nodes A, B, and C are precharged to a voltage 2VCC−Vth, the voltage VCC, and the voltage VCC, respectively, and the voltage of node D becomes VCC. When in this state, the signal CON1 of the power source voltage (VCC) is applied, the voltage of node A becomes VCC−Vth, and the voltage of node B increases to 2VCC. Then the NMOS transistor N7 will be in an on state and the voltage of node D becomes VPP−Vth. When the signal CON2 of power source voltage level is applied, the voltage of node A becomes VCC−Vth and the voltage of node C becomes VCC+VPP. Then the NMOS transistor N6 is turned on and the charge sharing operation is performed between node B and the high voltage generation terminal VPP to increase the voltage level of the high voltage generation terminal VPP. The NMOS transistor N8 is turned on, and the voltage of the high voltage generation terminal VPP is slowly increased. In other words, during the charge sharing operation, the NMOS transistor N8 is turned on to increase the voltage level of the high voltage generation terminal VPP, and then increase the voltage level of node D. That is, in the charge pump circuit of FIG. 3, when the signal CON1 is changed to the power source voltage VCC, the NMOS transistor N7 is turned on to increase the voltage of node D and the bulk of the NMOS transistor N6, and so reduce the voltage difference between the source and the bulk of the NMOS transistor N6. When the signal CON2 is changed to the level of the power source voltage VCC and the voltage of high voltage generation terminal VPP increases, the NMOS transistor N8 is turned on to increase the voltage of node D and the bulk of the NMOS N6 and so reduce the voltage difference between the source and the bulk of the NMOS transistor N6.
In the charge pump circuit of FIG. 3, the bulk (substrate) voltage of the NMOS charge transmission transistor is increased by an increase of source voltage so as not to increase the threshold voltage. Thus the charge transmission efficiency can be increased, but the following problems may be caused.
In FIG. 3, the bulk node D is connected to the node that has a low voltage level among the boosting node B and the high voltage generation node VPP to reduce a body effect, but when the voltage difference between node B and node D, or the voltage difference between node VPP and node D, is not larger than the difference corresponding to the threshold voltage that the NMOS transistor N7 and the NMOS transistor N8 respectively have, the NMOS transistors N7 and N8 are not turned on. In this case, node D will be in a floating state and the charge pumping operation may be uncertain. Thus, the increase of threshold voltage may not be prevented or reduced, degrading the charge transmission efficiency.
Accordingly, the body effect cannot be reduced due to the added transistors, as described aboven, and operation reliability is lowered by the floating state of bulk node.